1. Field of the Invention
The present invention relates generally to jitter tolerant retiming circuits, and specifically to a retiming circuit for accurately converting half-width dual rail data, with as much as one unit interval of data jitter, with respect to the input clock, into full-width signals. The invention is particularly advantageous in clock recovery circuits used in data transmission and in telecommunications transmission equipment.
2. Description of the Prior Art
The use of D-type flip-flops in the prior art to convert from half-width data to full-width data is well known. In such prior art circuits, a positive edge triggered D-type flip-flop is used to retime and convert half-width data on each rail (input data line) to full-width data. The half-width data is coupled to the D-input of the flip-flop and is clocked to the output of the flip-flop by the rising edge of the clock. For optimum operation of such a prior art circuit, it is required that the positive edge of the clock be in the middle of the data pulse such that error free operation is obtained with a maximum data jitter of plus or minus 0.25 unit interval with respect to the clock input.
A representative example of the prior art is U.S. Pat. No. 4,694,340, which describes prevention of jitter generation in a vertical synchronizing signal separating circuit. Another example of the prior art is U.S. Pat. No. 4,218,770, which describes the recovery of delay modulated data using a clock that is substantially faster than the data rate. Another example of the prior art is U.S. Pat. No. 4,017,803, which uses phase-lock loop techniques to maintain a desired relationship between data and the recovered clock.
Retiming circuits of the known prior art do not operate error-free when data jitter of 0.5 unit interval (UI) is present, hence such prior art retiming circuits must be configured to be very precise or to include additional circuitry to ensure that the input data and clock signals remain within 0.5 unit interval.
It is therefore an objective of the present invention to provide a retiming circuit that avoids the aforementioned disadvantages of the prior art, and enables an amplitude of jitter greater than 0.5 unit interval to be tolerated and accomodated without unnecessarily complex and costly circuitry.